In a multilayer circuit board, both wiring paths formed on both surfaces of an interlayer insulating film are connected to each other via a conductive portion formed to pass through the interlayer insulating film as needed. As one of methods for manufacturing such a multilayer circuit board, there is a method disclosed in Patent Literature 1, for example.
In this method, as illustrated in FIG. 6A, on a lower base plate 50 made of an insulator such as polyimide is deposited a conductive material via a seed layer 52 to form a lower wiring path 54 on the lower base plate 50.
Subsequently, an insulating bonding sheet 56 is coupled on an upper surface of the lower base plate 50 so as to cover the lower wiring path 54 (refer to FIG. 6B). On an upper surface of the bonding sheet 56 is fixed an insulator such as polyimide as an upper base plate 58. A via opening 60 opened to the lower wiring path 54 via this upper base plate 58 and the bonding sheet 56 is opened (refer to FIG. 6C). A conductive material is deposited in this via opening 60 to form a conductive portion 62 on the lower wiring path 54, and the conductive portion is exposed over the upper base plate 58 via an interlayer insulating film consisting of the bonding sheet 56 and the upper base plate 58 (refer to FIG. 6D).
Thereafter, a seed layer 64 is formed to cover upper surfaces of the conductive portion 62 and the upper base plate 58 (refer to FIG. 6E). The seed layer 64 facilitates deposition of a conductive material for an upper wiring path on the upper base plate 58. In this seed layer 64 is formed an opening 66 opened to the conductive portion 62 directly below the seed layer 64 by a selective etching process with use of an etching mask 68 (refer to FIG. 6F).
Also, on the seed layer 64 is formed an upper wiring path 72 burying the opening 66 and extending on the seed layer 64 by selective deposition of a conductive material with use of a new mask 70 to be formed after removal of the etching mask 68 (FIG. 6G). After removal of the mask 70, a part of the seed layer 64 exposed from the upper wiring path 72 is removed (FIG. 6H).
By doing so, a multilayer circuit board 74 having the lower wiring path 54 and the upper wiring path 72 mutually connected via the conductive portion 62 passing through the interlayer insulating film (56 and 58) as illustrated in FIG. 6H is formed.
In this multilayer circuit board 74, since the opening 66 reaching the conductive portion 62 is formed in the seed layer 64 prior to formation of the upper wiring path 72 as illustrated in FIG. 6F, no seed layer 64 lies between the conductive portion 62 and the upper wiring path 72. Thus, coupling between the conductive portion 62 and the upper wiring path 72 is not weakened, and the conductive portion 62 and the upper wiring path 72 can be coupled firmly.
Meanwhile, to form in the seed layer 64 the opening 66 allowing direct coupling between the conductive portion 62 and the upper wiring path 72, the etching mask 68 is used as described based on FIG. 6F.
FIG. 7A and FIG. 7B illustrate plan views of the process illustrated in FIG. 6(f). In the example illustrated in FIG. 7A and FIG. 7B, the conductive portion 62 has a rectangular horizontal cross-sectional shape, and an opening 68a analogous to the horizontal cross-sectional shape of the conductive portion 62 with a margin in consideration of an arrangement error is formed in the etching mask 68 formed on the seed layer 64. For example, when a lengthwise dimension (Y) and a breadthwise dimension (X) on the horizontal cross-section of the conductive portion 62 are 30 μm and 40 μm, respectively, and a lengthwise dimension (y) and a breadthwise dimension (x) of the opening of the etching mask 68 are 20 μm and 30 μm, respectively, a 10-μm tolerance is given to each of a longitudinal direction of the wiring path 72, which is an extending direction of the wiring path 72, and a width direction perpendicular to the longitudinal direction in terms of arrangement of the etching mask 68.
Accordingly, when the mask 68 is formed within this tolerance, the opening 68a of the etching mask 68 is arranged in an area corresponding to the horizontal cross-section of the conductive portion 62 as illustrated in FIG. 7A. Thus, by the selective etching process with use of the etching mask 68, the opening 66 to be formed in the seed layer 64 is opened in an area corresponding to the conductive portion 62 reliably. Consequently, in subsequent deposition of the conductive material for the upper wiring path 72, the conductive material is deposited in an area of the conductive portion 62 exposed to the opening 66 and on the seed layer 64 around the opening 66 reliably. Accordingly, the upper wiring path 72 filled with the conductive material and having a uniform width dimension is formed as illustrated by a dashed line in FIG. 7A.
However, there is a case in which an arrangement error occurs in a process of forming the etching mask 68 in a manner in which one side 68a-1 of the opening 68a of the etching mask goes over an edge represented by a corresponding side 62a of the conductive portion 62 and shifts in the extending direction of the upper wiring path 72 as illustrated in FIG. 7B. When such an arrangement error occurs, the seed layer 64 will be removed to go over the corresponding side 62a of the conductive portion 62 since an area of the seed layer 64 corresponding to the opening 68a of the etching mask 68 is to be removed. As a result, the upper base plate 58 below the seed layer 64 is exposed in an area A between the sides 62a and 68a-1, which goes over the corresponding side 62a of the conductive portion 62.
The conductive material for the upper wiring path 72 is not deposited appropriately on the area A, from which the upper base plate 58 is exposed, and thus the upper wiring path 72 to be formed by subsequent deposition of the conductive material for the upper wiring path 72 is provided with a void corresponding to the exposed area A of the upper base plate 58. Since this void extends in a direction of crossing the upper wiring path 72 and extends in an approximately entire length of a side 66a of the opening 66, the void significantly heightens an electrical resistance value of the upper wiring path 72 and easily generates disconnection of the upper wiring path 72.